1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits and semiconductor devices and, more particularly, to the manufacture of flash memory devices in the context of high-k/metal gate first technologies for manufacturing transistor devices.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, application specific integrated circuits (ASICs) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of electronic circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors (FETs), wherein, for many types of complex circuitry, MOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using, for instance, CMOS technology, millions of N-channel transistors and P-channel transistors are formed on a substrate including a crystalline semiconductor layer.
There are basically two well-known processing methods for forming a planar or 3D transistor with a high-k metal gate (HKMG) structure. In the replacement gate technique, a so-called “dummy” or sacrificial gate structure is initially formed and remains in place as many process operations are performed to form the device, for example, the formation of doped source/drain regions, performing an anneal process to repair damage to the substrate caused by the ion implantation processes and to activate the implanted dopant materials. At some point in the process flow, the sacrificial gate structure is removed to define a gate cavity where the final HKMG gate structure for the device is formed. Using the “gate first” technique (HKMG first), on the other hand, involves forming a stack of layers of material across the substrate, wherein the stack of materials includes a high-k gate insulation layer, one or more metal layers, a layer of polysilicon, and a protective cap layer, for example, silicon nitride. One or more etching processes are performed to pattern the stack of materials to thereby define the basic gate structures for the transistor devices.
A flash memory device (for example, a FLASH EPROM or FLASH EEPROM) is a semiconductor device that is formed from an array of memory cells (devices), with each cell having a floating gale transistor. Flash memory chips fall into two main categories, namely, those having a so-called “NOR” architecture and those having a so-called “NAND” architecture. Data can be written to each cell within the array, but the data is erased in blocks of cells. Each floating gate transistor comprises a source, drain, floating gate and control gate. The floating gate uses channel hot electrons for writing from the drain and tunneling for erasure from the source. The sources of each floating gate in each cell in a row of the array are connected to form a source line. In embedded memory solutions, memory cells are provided in the neighborhood of logic devices and are, particularly, together with the logic devices on a single (monolithic) silicon substrate. Flash memory devices are used in many applications, including hand-held computing devices, wireless telephones and digital cameras, as well as automotive applications. To enable the individual memory elements of a flash memory chip to maintain the physical state with which they have been programmed, each memory region must be isolated from its neighboring regions, typically, by shallow trench isolations.
Whereas flash cell integration in the context of manufacturing of field effect transistors (FETs) with silicon-oxynitride gate dielectrics can be reliably achieved, integration of flash cells in HKMG technology used for the formation of FETs still poses challenging problems. After patterning, the metal gate electrodes have to be protected against cleaning processes by encapsulation and the gate dielectric layers are to be protected against oxidation as far as possible in order to avoid significant variations of the threshold voltages of the FETs. Reliable encapsulation by sidewall spacers demands a smooth topology over active and shallow trench isolation regions of the wafer. These aspects have to be taken into account when considering the integration of memory cells within the HKMG technology used for the formation of FETs.
A variety of single gate and split gate solutions for embedded memory cell architectures are known in the art. FIG. 1 illustrates an embedded super flash cell that is known in the prior art. The cell is formed on a semiconductor substrate 11 wherein source/drain regions 12 are formed. The cell comprises a floating gate 13, a control gate 14, an erase gate 15 and a select gate 16 formed by a word line. All gates may be made of polysilicon and they are covered by a multilayer insulation structure 17. The multilayer insulation structure 17 comprises parts of spacer structures formed on the tops and sidewalls of the gates. The floating gate 13 is formed over a floating gate oxide layer 18 and it is separated from the erase gate 15 by a tunnel oxide layer 18a that may be formed of the same material as the floating gate oxide layer 18. The control gate 14 and the floating gate 13 are separated from each other by an isolation layer 19, for example, an oxide-nitride-oxide (ONO) layer provided in order to enhance the capacitive coupling between the floating gate 13 and the control gate 14.
Whereas memory cells as the one illustrated in FIG. 1 are considered to be reliable operating devices, they cannot be readily integrated in the conventional process flow of HKMG technologies. According to the conventional process flow, a floating gate layer is formed over a semiconductor substrate (in particular, on a floating gate oxide formed on the surface of the semiconductor substrate). A shallow trench isolation (STI) is formed in the semiconductor substrate and the floating gate layer is patterned. The STI separates a region designated for the formation of logic devices from a region designated for the formation of a memory cell. The subsequently performed flash cell formation/patterning includes the deposition of an ONO layer (oxide-nitride-oxide) on the patterned floating gate layer and the deposition of a control gate layer on the ONO layer followed by patterning of the control gate layer. Further processing includes spacer formations and removals, formation of an erase gate layer and a tunnel oxide and the patterning of the erase gate layer. A select gate and a logic gate of a logic device are formed by deposition and patterning of a suitable material layer. Silicidation of electrodes and electrically contacting the silicided electrodes (gate, source, drain) as well as some Back-End-of-Line processing follow.
This overall conventional processing has a severe impact on the topology of the STI area. Between the deposition of the control gate layer and the patterning of the select gate, many etching and cleaning steps are needed that affect the STI area, giving rise to an uneven STI. The uneven topology of the STI area leads to some remaining HKMG material outside the gate electrode stack in the logic area after gate patterning. This residual HKMG material cannot be properly covered by sidewall spacers formed to protectively encapsulate the gate electrode-high-k gate dielectric stack. The residual high-k material outside the stack must be removed by a cleaning step before halo implantation, implantation of source/drain extension regions, etc. However, this cleaning step removes not only high-k material outside the stack but also material of the high-k gate dielectric below the gate electrode of the FET that is formed in the logic area of the wafer, thereby heavily affecting operation and reliability of the resulting semiconductor device.
In view of the situation described above, the present disclosure provides a technique of forming a semiconductor device comprising memory cells integrated within HKMG technologies without causing a pronounced STI topology and, thereby, resulting in an improved reliability and enhanced operational characteristics of the resulting semiconductor device.